Multimedia Design Verification Engineer, Silicon
- Banqiao, New Taipei City
- Permanent
- Full-time
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience with verification methodologies and languages such as UVM or SystemVerilog.
- Experience in verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience creating and using verification components and environments in a standard verification methodology such as UVM.
- Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
- Experience with image processing or other multimedia IPs such as Display or Video Codec.
- Experience with verification techniques, System Verilog Assertions (SVA), and assertion-based verification.
- Experience with GLS, low-power DV, and support of SOC DV.
- Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.