Senior Digital Design Verification Engineer - Hardware
Nvidia
Hsinchu City
Permanent
Full-time
1 month ago
We're now looking for a Senior Digital Design Verification Engineer!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join our diverse team today!As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a best-in-class team that delivers IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols!What you’ll be doing:Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.Write and execute test plan and thoroughly verify a design in a product shipment focused / compressed schedule.Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.What we need to see:Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer EngineeringAt least 5 years of proven experience.Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.Ways to stand out from the crowd:Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a big plus.Experience in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits a big plus.Perl, Python, C/C++ programming language experience.Good debugging and analytical skills.Good communication skills & dream to work as a great teammate.
