Lead Design Engineer -- Memory Modeling Portfolio
Cadence Design Systems
- Hsinchu City
- Permanent
- Full-time
- Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM, NAND Flash, eMMC, DFI PHY, and UFS models for use on hardware based verification products.
- Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.
- Perform as individual and collaborative contributor for RTL design, verification, productizing, and documentation of memory IP.
- Requires a collaborative temperament, articulate and proactive expression of ideas, and good communication skills with diverse behavioral styles.
- Interface with internal and external customers to work on diverse problems and solutions related to use of memory model IP in emulation or verification.
- As a team member and collaborator working with folks in a fast-moving industry, this role requires flexibility, adaptability, curiosity, energy, and stability with an open listening heart and a “YES” brain.
- Team member will develop and use lifecycle processes to ensure product quality.
- RTL design knowledge using Verilog/SystemVerilog is required
- Experience in protocol-based development
- Hands-on experience using RTL verification tools and flows
- Demonstrable debugging experience is critical
- Familiar with team-wide collaboration tools and process
- Drive and ability to schedule workload and plan own tasks effectively
- Verification experience using Cadence simulation and/or emulation products
- Programming experience with scripting languages like Perl, TCL, C-shell
- Knowledge of memory sub-system design and operation