3+ or more years of semiconductor process or equipment engineering experience, package CMP, Grinding, dicing, reflow equipment. (equipment ex: AMAT/LAM/DISCO ) Develop hardware roadmaps for 5+ years in the area of post probe wafer and die processing. Optimizing equipment to reduce cost, availability, and improve hardware and process capability. Collaborating with process development teams to develop innovative new solutions. Conducting root cause and failure mode analysis to understand the limitations of current hardware and drive APTD development projects with OEMs vendors for solutions. Performing fundamental research to drive innovative solutions for next-generation equipment products. Support equipment transfer to production facilities (some domestic or international travel may be required). Experience with design of experiment techniques (DOE), Statistical Process Control (SPC), Defect analysis and data analysis Strong analytical and creative problem-solving skills. Ability to use extensive technical knowledge to guide strategic directions. Ability to resolve complex issues through root-cause or model-based problem solving. Proficiency in statistics, preferably in statistical process control. Ability to work independently, with minimal direction, and a focus on meeting commitments. Ability to multi-task and manage numerous projects simultaneously. Hands on experience with wafer / assembly tools and overlay systems. M.S./Ph. D. (or equivalent education) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or other related technical fields. 2 or more years of semiconductor process or equipment engineering experience, preferably in wafer bonding, plating, warpage control and packaging field Experience in equipment development with fundamental understanding of post probe and assembly process and equipment interactions. Experience in wafer bonding, plating, warpage control and packaging process development and understanding of related inline/electrical/probe failure. Knowledge of semiconductor processing, solid-state device physics desirable.
