Platform Memory Controller Architect, Silicon
- Banqiao, New Taipei City
- Permanent
- Full-time
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in a memory controller architecture/micro-architecture.
- Experience in ASIC architecture performance analysis, tools, and simulators at different abstraction levels (e.g., Cycle Accurate, TLM, or Functional).
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with coding in C/C++/Python.
- Experience working with 3rd-party vendor solutions.
- Experience designing/implementing or validating RTL for Fabric, MMUs, Caches, or memory controllers.
- Knowledge of HDL languages such as System Verilog, Verilog.
- Knowledge of Coherent interconnects, Caches, or memory system.
- Explore and evaluate the architectural design choices for DRAM memory controller and whole memory system.
- Build hardware architectural specification for next-generation memory controller IP.
- Work with other hardware and software architects to understand and improve the architecture.
- Develop C-models, simulate/analyze performance and power trade-offs.
- Work with Hardware design, verification, emulation, and validation teams to build and test the hardware architecture.