Principal Engineer, Design Verification

Marvell

  • Hsinchu City
  • Permanent
  • Full-time
  • 15 days ago
About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.Your Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc.What You Can ExpectIn this role, you will develop the architecture for a functional verification environment, including SerDes, and PCIe PHY and contribute to the methodology behind such development.
Activities may include:
  • Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
  • Developing tests and tuning the environment to achieve coverage goals.
  • Debugging failures and working with designers to resolve issues.
  • Collaborate closely with design, architecture, and software teams to understand specifications and drive first-pass silicon success.
  • Expected to work independently, take initiative, and adapt quickly in a fast-paced environment.
What We're Looking For
  • Master Computer Engineering, Electrical Engineering, or Computer Science with 12+ years of Design verification experience (or PhD with 8+ years' experience).
  • Experience with System Verilog, UVM.
  • Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
  • Experience with scripting language such as Python or Perl and EDA Verification tools.
  • Experience with Object-Oriented Design and implementation.
  • Good programming skills desired, especially C++ and ARM assembly.
  • Understanding of Ethernet, Serdes, PCIE PHY DV, a plus.
Other Skills:
  • Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
  • Requires the ability to accept and work with differing opinions.
  • Cannot be a close-minded developer.
  • Must be able to learn on the fly and work in a fast-paced environment.
Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.#LI-SYU

Marvell