This is a senior level position. Minimum 5 years of relevant working experience is required. Master's or Ph.D. degree in Physics or Engineering areas is preferred. Working experience in wafer fab process or process integration engineering. Direct experience in advanced CMOS device technology such as FinFET or GAA is preferable. Proven knowledge in semiconductor physics and understanding of transistor operations, scaling limitations and reliability, basic knowledge of CMOS circuits and characterization methods. Understanding of wafer fabrication process areas, including tool sets, process mechanism, tuning knobs, etc. Excellent data analysis skills using software (JMP, SPOTFIRE, etc). Strong task ownership, self-motivated to work with other team members to make progress collaboratively. Open-minded attitude to learn new skills and could adapt to new working environment swiftly. Good communication skills. Proficient in English (speaking and written). Working-level communication capability in Mandarin Chinese OR Japanese is preferred. Good digital literacy with MS office. Programming capability such as Python is a plus.
