ASIC Architect, Silicon
- Banqiao, New Taipei City
- Permanent
- Full-time
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in ASIC performance power management or low-power design and methodology.
- Experience in computer architecture concepts, such as micro-architecture, cache, pipe-lining, and memory subsystems.
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience designing, implementing, or validating in two or more areas such as Coherent fabrics, Caches, Fabrics, IOMMUs, QoS, or Memory Systems.
- Experience in SoC architecture performance analysis, tools, and simulators (e.g., Cycle Accurate, TLM, or Functional).
- Experience with C or C++.
- Experience in SoC system pre-silicon or post-silicon performance analysis and tuning.
- Knowledge of HDL languages such as System Verilog, Verilog.
- Work with internal stakeholders to define IP, Subsystem and ASIC specifications to meet PPA requirements.
- Collaborate with internal cross-functional teams on pre-silicon performance/power analysis, evaluating design trade-off, writing test and validation plans, and resolving implementation issues.
- Work with cross-functional teams on post-silicon chip bring-ups and on performance, power, and functional issues.
- Perform analysis results in both qualitative and quantitative fields.
- Participate in evaluation of future ASIC designs and general architecture.