Staff Engineer, Physical Design

• Engage in hands-on physical design and verification tasks across various projects in advanced process nodes.
• Manage the setup and maintenance of project-specific ASIC development flows.
• Execute physical design tasks including floor-planning, place and route, clock tree synthesis (CTS), timing closure, IR/EM analysis, and logical equivalence checking (LEC) for both block-level and full-chip designs, coordinating all physical design and verification activities.
• Conduct physical verification tasks, including creating setups and scripts for DRC, LVS, DFM, antenna and density checks, as well as report generation, analysis, debugging, and implementing fixes in the physical design database.
• Preferred experience with high-speed designs at 2.5GHz and above.
• Report to the Senior Director of ASIC Design.
• Mentor junior physical design/verification team members and oversee their tasks.

• A minimum of 15 years of experience in ASIC/SoC physical design.
• Proficiency in advanced FinFET node designs.
• Experience with Cadence/Synopsys place and route (PnR) and static timing analysis (STA) tools, as well as Calibre; strong scripting and automation skills are essential.
• Education: B.Tech/M.Tech in Electronics Engineering.

Morgan Philips