
Staff Digital Verification Engineer
- Jhubei, Hsinchu County
- Permanent
- Full-time
- Define testbench infrastructure using SystemVerilog, UVM and Formal.
- Responsible for complete digital level verification.
- Modeling of analog functions in SystemVerilog.
- Responsible for complete chip level verification of mixed signal IC.
- Work closely with design team to architect a new design verification environment and produce high quality verification closure.
- Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
- 8+ years of experience in ASIC/IC verification.
- Experience in UVM based verification flow.
- Experience in system Verilog
- Experience in SimVision or Verdi debug skills.
- Familiar with scripting language like Makefile, Perl, Tcl or Python.
- ownership of unit level testbench built from scratch to coverage closure
- Good understanding of OOP concepts
- Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.
- experience with multi-unit level testbench and/or SoC/chip level testbench, including integrating ULTB and handling multiple sequence libraries or agentes' driving
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.