
Principal Engineer, ASIC Verification Engineering
- Jhubei, Hsinchu County
- Permanent
- Full-time
- Develop and execute verification plans for complex ASIC designs
- Create and maintain testbenches using SystemVerilog and UVM
- Design and implement efficient verification environments
- Perform functional and formal verification of digital designs
- Develop automated test scripts to improve verification efficiency
- Analyze and debug design issues identified during verification
- Collaborate with design engineers to resolve functional discrepancies
- Generate detailed verification reports and documentation
- Stay updated with industry trends and emerging verification methodologies
- Contribute to the continuous improvement of verification processes and tools
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of experience in ASIC verification with strong proficiency in SystemVerilog and UVM
- Experience with Verilog, VHDL, and industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
- Experience of CPU, GPU, NPU or HBM verification
- Knowledge of formal verification techniques and tools
- Strong debugging, problem-solving, and analytical skills
- Solid understanding of digital logic design, computer architecture, and communication protocols
- Excellent organizational skills with strong attention to detail
- Good communication and teamwork skills in a fast-paced environment