【2024 Campus Recruitment】TSMC IIP Engineer

台積電

  • Taiwan
  • Permanent
  • Full-time
  • 2 months ago
Job ResponsibilitiesAs a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer's variety applications.Integration:1. Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline.2. Package level reliability, failure mode analysis and improvement plan.3. Customer technical interface, new tape out and lot handle.4. Handover developed technologies to manufacturing groups for production.Module Development:1. Be responsible for CVD / PVD / CMP / Lithography / Etch / Polymer / Bonding / Clean module development for 3DIC projects.2. New technology, materials survey, and process improvement on 3DIC package structures.3. Process development and tool transfer to mass-production development.Simulation:1. Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment.2. Practice FEM and DOE in problem solving and path finding particularly on packaging.3. Continue improvement in simulation methodology, material modeling and script automation.Job Qualifications1. Master's degree or above in Chemical Engineering, Material Science, Chemistry, Physics, Mechanical Engineering, or related field in science or engineering2. Experience in TV design or IC packaging is a plus3. Good communication skills in Chinese and English4. Hands-on participation and a strong sense of ownership are required5. Strong technical problem-solving and analytical skills6. For simulation positions, mastery of FEM software such as Ansys, LS-DYNA, Abaqus and others

台積電