【2026 TSMC RDSS & AO】Advanced Packaging Technology and Service Engineer (APTS)

台灣積體電路製造股份有限公司(台積電)

Baoshan, Hsinchu County
$40,000 per month
Permanent
Full-time

1 month ago

職缺描述【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16576&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers' products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world's largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: TSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc. This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration. TSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution. TSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields. TSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device (logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.收合內容工作待遇面議 (經常性薪資達4萬元或以上)查看薪資水平職務類別半導體工程師工作性質全職工作時間日班休假制度週休二日工作地點新竹縣寶山鄉（新竹科學園區）要求條件學歷要求大學以上科系要求工作經驗不拘外語能力
聽｜精通、説｜精通、讀｜精通、寫｜精通工作技能不拘附加條件1. Bachelor's degree or above in Electrical/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields. 2. Solid technical understanding of semiconductor testing concept. 3. Familiar with programming language. 4. Hands-on participation and a strong sense of ownership. 5. Fluent in English and exhibit good communication skills to work within cross-functional teams.展開全部歡迎身份歡迎所有求職者公司資訊公司名稱品牌名稱產業類別

半導體製造

聯絡資訊聯絡人員招募處備註【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=16576&source=1111&tags=AO+2026_1111

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